To tackle the increasing complexity of digital electronic circuits, designers need faster methods of simulating such circuits, particularly in light of ever-shrinking product development times.
The complexity of designing such circuits is often handled by expressing the design in a high-level hardware description language (HDL) such as Verilog.
High-level HDLs allow the designer to save design time by permitting him or her to express the desired functionality at the register transfer level (RTL) of abstraction or higher. The high-level HDL description is then synthesized into an actual circuit through a process, well known to those of ordinary skill in the art, of translation and optimization.
High-level HDLs describe, directly or indirectly, the two main kinds of circuit entities of an RTL circuit description: i) state devices or sequential logic which store data upon application of a clock signal, and ii) combinational logic. The state devices typically act as either: i) an interface between conceptually distinct circuit systems, or ii) storage for the results of functional evaluation performed by the combinational logic.
In order to verify the functionality of such high-level HDL descriptions, it is usually desirable to simulate the circuit thereby produced before actually manufacturing it.
Simulation can occur at a variety of levels of modeling abstraction. Known example levels of modeling abstraction are: transistor, gate, register transfer and behavioral. Typically, the lower the level of abstraction, the more accurate the simulation. Typically, however, the lower the level of abstraction the greater is the amount of time required to perform the simulation.
Simulation time can be a significant limitation upon a designer's ability to explore a variety of design alternatives and therefore it is almost always desirable to achieve a simulation time which is as short as possible.
Conventional simulators assume that the level of simulation activity, throughout a design to be simulated, is uniform. Simulation activity is determined by the rate at which signal levels, within circuit elements being simulated, change. If the level of activity is assumed to be uniformly low, then it is desirable to simulate using an event-triggered mode in which evaluation is performed only for those circuit elements whose signal levels are changing. Alternatively, if the level of activity is assumed to be uniformly high, then it is desirable to simulate using an oblivious cycle-based mode in which all circuit elements are evaluated upon every clock cycle since the scheduling overhead inherent in any event-triggered approach is avoided.
However, typical designs have non-uniform activity levels due to their components having different characteristics. Examples of different types of components, each of which is often associated with a different level of simulation activity, are: controller unit, datapath unit, memory unit and input/output unit.
Therefore, certain regions of a digital electronic system may have high levels of simulation activity, while other regions of the system may have low levels of activity.